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IBM39STB0210x
Advance STB0210x Digital Set-Top Box Integrated Controllers
Features
Overall * IBM Set-Top Box technology * Four major subsystems integrated with IBM onchip CoreConnectTM structure. * Maximum MIPS for OS and application tasks * Simplified driver and software development * Scalable, flexible, and extendible * 54 MHz/57 MIPS * 3.3 V and 2.5 V power supplies * IBM CMOS SA-12E process(0.25 m) * 352-pin PBGA package MPEG-2 Digital Audio/Video Subsystem * MPEG-2 Video Decoder * MPEG-2 Audio Decoder * MPEG-2 Transport/DVB Descrambler * Macrovision Copy Protection on selected parts * Display Controller * Digital Encoder (DENC) with six outputs * Anti-Flicker Filter PowerPC 401TM Host Processor: PPC401B3 CPU * 16KB Instruction, 8KB Data caches * Universal Interrupt Controller Memory Subsystem * DMA Controller * Cross-Bar Switch * External Bus Interface Unit (EBIU) * IDE Interface * One SDRAM Controller Peripheral Subsystem * General Purpose Timers (GPTs) * Pulse Width Modulators * Smart Card controller * I2C Interface * 16550 Serial Communications Port * Infrared Serial Communications Port * General Purpose Inputs/Outputs * Serial Controller Port * Modem Serial Interface/Digital Audio Input
Description
IBM STB0210x Digital Set-Top Box Integrated Controller family are highly integrated silicon devices specifically developed for digital set-top box (STB) applications using industry-leading IBM CMOS SA12E (0.25 m) process technology. The STB0210x is part of the second generation of IBM products for digital STB applications. PowerPC processing and peripheral I/O architecture provide a high level of performance and functionality when used in audio and video subsystems. The resulting STB technology is full-functioned and easy to use. The STB0210x minimizes host processor intervention to maximize MIPS for operating system and application tasks. Most of the features required in the back end of typical midrange and high-end STBs are integrated. Driver and software development is facilitated while preserving scaleability, flexibility, and extendibility. Architecturally, the devices consist of four subsystems interconnected and tuned using CoreConnect, the IBM multiple-bus, on-chip interconnect structure: 1. PowerPC host processor 2. Digital audio/video 3. Memory interface 4. Peripheral These high performance subsystems are suited for interactive STBs with demanding software requirements.
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Features
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Ordering Information
Part Number IBM39STB02100PBA22C IBM39STB02101PBA22C1 57 MIPS 54 MHz MPEG Macrovision Performance (est.) Clock Speed Audio Copy Protection None
1. These parts support Macrovision Copy Protection and require that a license be in effect between the purchaser and Macrovision Corporation. Please see "Macrovision Licensing" on page 3.
Conventions and Notation
Throughout this document, standard IBM notation is used, meaning that bits and bytes are numbered in ascending order from left to right. Thus, for a 4-byte word, bit 0 is the most significant bit and bit 31 is the least significant bit. Overbars, e.g. TxEnb, designate signals that are active low. Numeric notation is as follows: Hexadecimal values are in single quotes and preceded by "x" or "X." For example: x'0B00'. Binary values are spelled out (zero and one) or appear in single quotes and preceded by a "b." For example: b`10101'. Settings of a bit or field are binary numbers but are often displayed in tabular form without quotes or the preceding "b." For example: 00 : 30 frames per second 01 : 15 frames per second 11 : 10 frames per second
Ordering Information
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Licensing Requirements
Macrovision Licensing
Macrovision Copy Protection is supported in the IBM39STB02101 product. These devices are protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property rights. The use of Macrovision's Copy Protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. A valid Macrovision license must be in effect between the STB02101 purchaser and Macrovision Corporation. Additional per-chip royalties may be required and are to be paid by the purchaser to Macrovision Corporation. Macrovision Corporation 1341 Orleans Avenue Sunnyvale, CA 94089
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Architecture and Subsystem Information
Block Diagram
Interrupts SRAM JTAG TRACE UIC PPC401B3 CPU 16K-I 8K-D Cache Cache EBIU DMA Controller
IDE PERH DEVICE FLASH ROM
OPB Bus
GPT PWM
Smart Card1
OPB Bridge
PLB0 Crossbar PLB1 SDRAM1 Controller
SDRAM
I2C0
Transport DVB Descrambler
Serial0/ 16550 Serial1/ Infrared
NIM Descrambler
GPIO Serial Control Port Modem Interface Video Decoder OSD Digital Encoder DAC Ext Digital Encoder 2D/3D Graphics Audio Decoder
Audio D/A
IEC-60958
Architecture and Subsystem Information
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PowerPC 401B3 Host Processor Subsystem
The PowerPC 401B3 (PPC401B3) subsystem handles all system initialization and control and also provides power and flexibility for product differentiation. PPC401B3 Subsystem
PPC401B3 Processor CPU UIC Interrupt Controller Interface Timers: PIT, FIT, 64-bit base Multiplier/Divider Interrupts RISC Execution Unit Core Clocking Thirty-two 32-bit GPRs Clocks Power Mgmt DCRs JTAG (See Note) Interfaces
MMU 16KB I-cache Array Instruction Cache Controls Data Cache Controls
8KB D-cache Array
PLB Master
PLB Master
Note: The JTAG interface is used for development.
PowerPC 401B3 CPU The PPC401B3 provides high performance and low power consumption. The CPU executes at sustained speeds of greater than one cycle per instruction at 54 MHz. Interrupt latency is three cycles, the best time for critical interrupts.
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On-chip instruction is compatible with PowerPC User Instruction Set Architecture. There are 32 x 32 bit general purpose registers. Instruction and data cache arrays improve system throughput. The CPU has a separate two-way set-associative 16KB instruction cache and an 8KB write-back/write-through data cache. Multiply and divide instructions are performed in hardware and are not emulated in software. Universal Interrupt Controller The Universal Interrupt Controller (UIC) provides all necessary control, status, and communication functions between all sources of interrupts and the PPC401B3. The UIC combines STB0210x interrupts and presents them to the PPC401B3's critical or non-critical inputs. All interrupts can be programmed to generate either critical or non-critical output. Interrupts can be level- or edge-sensitive and interrupt polarity is programmable. An optional read-only vector is used to reduce critical interrupt servicing latency. This vector is generated by combining an offset (based on the bit position of the highest priority, enabled, and active critical interrupt) and a vector base address register. A configurable priority control bit determines whether the least significant or most significant bit in the status register has the highest priority. Clock and Power Management For power-saving purposes, a Clock and Power Management (CPM) input is used to shut down clocks and device functions. A reset is required to activate a unit.
Memory Interface Subsystem
The memory interface subsystem provides the system memory controller interface for SRAM, FLASH Memory, ROM, and SDRAM. It also provides the Direct Memory Access (DMA) interfaces for these memories. Memory Subsystem
DMA
EBIU
FLASH, ROM, etc.
PLB0 Crossbar PLB1 SDRAM SDRAM1
Direct Memory Access Controller
The four-channel DMA controller is a processor local bus master that allows faster data transfer between memory and peripherals than with program control. The controller supports memory-to-memory, peripheralto-memory, and memory-to-peripheral transfers. The DMA controller allows the PPC401B3 processor to execute instructions with no bus contention when the PPC401B3 is executing from cache. DMA is useful when the overhead associated with the controller setup is minimal compared to the time it would take to move data using program control load and store instructions.
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Each DMA channel has an independent set of registers for data transfer. The registers store data for control, source address, destination address, and transfer count. Each channel also supports chained DMA operations, therefore every channel also includes a chained count register in which case source address registers function as chained address registers. All DMA channels report their status to the DMA execution unit. The DMA controller also supports: * Internal DMA channels for smart card interface, 16550 serial communications controller, infrared communications controller, etc. * 16- and 32-bit peripherals (on-chip peripheral bus and external) * 32-bit addressing * Address increment or decrement * Internal data buffering capability * Memory-mapped peripherals Processor Local Bus The Processor Local Bus (PLB) interfaces directly with the PPC401B3 and the other major subsystems (see "Block Diagram," on page 4). The STB0210x uses two PLBs to provide high bandwidth between the function masters and the external memory interfaces for ROM, Flash, and SDRAM, etc. The STB0210x PLB architecture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces. External Bus Interface Unit The External Bus Interface Unit (EBIU) expands the local bus to transfer data between the PLB and a wide range of memory and peripheral devices attached to the external bus (see the following list). The EBIU can control up to eight devices or banks or regions of FLASH memory (128 MB), and a low latency maximizes system performance. The EBIU supports: * A direct connect SRAM/ROM/PIA interface for - up to eight SRAM/ROM/PIA banks with programmable address select - programmable or device-paced wait states - burst mode (BME) and single-cycle transfers * 16- and 32-bit byte addressable bus width * Programmable target word first or sequential cache line fills * DVB Common Interface Support * IDE interface supports: - ATA-3 mode 4, register, and PIO - Mode 2 Multiword DMA transfers (see ANSI X3.298-1997, AT Attachment-3 Interface (ATA-3)) - Multi-word DMA (15.5 MB/s maximum transfer rate) * External bus master with support for device master and master/slave * Common bank-specific programmability * Device-paced ready input SDRAM Controller The SDRAM Controller transfers data between the PLB and up to two SDRAM memory banks attached to the external bus. The Controller implements address and data pipelining and supports 16Mb and 64Mb SDRAMS concurrently. It also provides the following: * Direct-connect SDRAM interface
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* * * * *
High bandwidth with a narrow 16-bit interface Page interleaving Programmable address select Programmable rates for automatic SDRAM refresh Software-initiated and self refresh modes for power savings
Crossbar Switch
The PLB Crossbar Switch (CBS) creates a flat memory model and implements Unified Memory Architecture (UMA), which connects multiple PLB master buses to the PLB slave buses, thus allowing two sets of PLB buses to intercommunicate. Processor, transport, and the audio and video decoders can access memory through the memory controller.
Digital Audio/Video Subsystem
The MPEG-2 Digital Audio/Video subsystem provides fully-synchronized playback of digital video and audio programs, with a minimum of interaction from the PPC401B3 processor.
DVB Descrambler
Audio PLL to Audio D/A and IEC60958 MPEG-2 Audio Decoder
VCXO
NIM
Auxiliary
MPEG-2 Transport
MPEG-2 Video Decoder OSD
Auxiliary Port
DENC PLB0
MPEG-2 Video Decoder with OSD The MPEG-2 video decoder provides decompression, decoding, and synchronized playback of digital video streams with a minimum of host support. It produces interlaced video output and can support MPEG-2 compressed data streams up to an average rate of 15 Mbps. The video decoder is also backward compatible to support the ISO/IEC International Standard 11172-2 (11/93) (also called "MPEG-1 Standard"). It supports the ISO/IEC 13818-2 Main Profile at Main Level. The decoder also supports MPEG-2 MP@ML compliance with 2MB memory. Only 2MB of memory are needed to decode full CCIR601 resolution NTSC and PAL encoded MPEG-2 bitstreams. It performs real-time decoding of all resolutions in 16-pixel multiples, up to and including 720x480x30 or 720x576x25. Horizontal and vertical filters deliver high-quality video. Chrominance filtering and up-sampling to provide CCIR601 4:2:2 video output. Pan and scan are supported in 1/16 pel accuracy for 16:9 source material. Video rates range from 1.5 Mbps to 15 Mbps (higher in bursts).
Architecture and Subsystem Information
PLB1
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The MPEG-2 video decoder supports the European DVB standard and accepts Packetized Elementary or Elementary MPEG-2 streams. It uses Packetized Elementary Stream (PES) video decoding to extract the Presentation Time Stamp (PTS), and handles user data and other PES layer bit fields through memory access from the PPC401B3. Input can be from transport or directly from system memory. Outputs are provided for video-only and for video-with-OSD. The decoder can insert data in the vertical blanking interval (VBI) with VBI Output Support. It supports decoding of still or fixed images and display of scaled video images. It also features: * * * * * * * * * * * * * Letterbox format display Selectable anti-flicker filtering Output interface flexibility (programmable controls) Composite blanking and Field ID signals V-sync and H-sync signals CCIR656 master and slave modes Programmable signal polarity Sophisticated error concealment 3:2 pull-down support. Closed caption, teletext, or mixed (VPS) (1/4x, 1/2x, 2x) and three graphic planes Automated video channel change and time-base change features Blending of external graphics.
A multi-plane on-screen display (OSD) uses bitmap data in memory to be merged with or displayed in place of the motion video data. Three OSD planes (the cursor, graphics and image planes) are provided for increased display flexibility. The OSD includes: * * * * * * * * * * * * * Programmable background color Multi-region link list graphic and image plane OSD with a color table for each region Programmable bitmap resolution on a region-by-region basis 64 x 64 pixel, 16-color cursor plane with blending controls Overlay and video blending of graphic plane Enhanced color mode for 24-bit color (YUV) in Direct Color and CLUT modes with 8-bit alpha blending Video shading in graphic plane OSD area OSD control output for external multiplexer (picture-in-picture support) Tiling capability in image and graphic planes Scrolling of image and graphic planes Horizontal scaling of image plane bitmaps Animation support 16 MB OSD addressing range to support more and larger bitmaps.
MPEG-2 Transport and DVB Descrambler The MPEG-2 transport demultiplexer provides ISO / IEC 13818-1 MPEG-2 transport system layer demultiplexing. Its integrated digital video broadcasting (DVB) descrambler complies with DVB system layer requirements and may be turned off for non-DVB applications. Peak input rates are 100-Mbps (parallel) or 60-Mbps (serial), or 88-Mbps (parallel) or 60-Mbps (serial) with the optional descrambler. Packet Identifier (PID) filtering is based on 32 programmable entries with detection and notification of errors and lost packets. Hardwarebased clock recovery on program clock references (PCRs) reduces processor load by: - Calculating clock difference between PCR and System Time Clock (STC) - Modulating output to drive an external VCXO - Using an optional internal clock-recovery algorithm based on clock difference
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Transport and descrambler features include: * Internal DVB (1.0 or 1.1) descrambler, including filtering and storage of eight control word pairs * Auxiliary output port for real-time data transfers: - 8-bit mode at 1X, 1/2X, 1/3X, 1/4X and 1/8X of the system clock speed * Table section filtering: - 64 separate 4-byte filter blocks with bit-level masking with full match/not match capability - Multiple filters can be linked to extend filtering depth in 4-byte increments - Multiple filters per PID - Filters program-specific information (PSI), service information (SI), private tables - Handles multiple sections per packet and sections that span packets - Optional CRC checking of section data * Selective routing of some or all packet data to system memory: - Based on 32 separate queues (one per PID) - Routing entire packets, payloads, adaptation fields, table sections (after filtering) and private data * Direct transfer of audio / video (PES) data to decoders * Simplified channel changes, time-base changes and error flagging / concealment through direct communication with decoders MPEG-2 Audio Decoder The Audio Decoder receives and decodes either ES (Elementary Stream) or PES (Packetized Elementary Stream) audio data. The audio compute engine is a generic DSP processor that decodes MPEG, or 16-, 18or 20-bit unformatted Pulse Code Modulation (PCM) audio data via individual software programs. The host processor downloads each program load to the Audio Decoder following initialization. The Audio Decoder generates up to two channels of decoded PCM for MPEG and PCM audio playback output. It provides 2-channel MPEG audio to two channels output. Unpacketized PCM (UPCM) plays back at sampling frequencies of 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, and 48 kHz, along with quantization sample width selections of 16-, 18-, or 20-bit input and 16 or 20-bit output. The Audio Decoder: * Decodes MPEG-1 and MPEG-2 audio, Layers I and II and 2-channel output, including single channel, stereo, joint stereo, and dual channel modes. * Performs MPEG-1 and MPEG-2 PES audio parsing, and also accepts audio elementary streams. Parses and stores ancillary data into external memory for later use by the host processor. * Supports 16-kHz, 22.05-kHz, 24-kHz, 32-kHz, 44.1-kHz, and 48-kHz audio sampling frequencies. * Supports audio/video synchronization through PTS/STC comparison with each audio frame. * Supports an encoded audio bit rate up to 640 Kbps. This bit rate only pertains to encoded bitstream data. * Includes Audio Clip Mode for PES, ES, and PCM formats with byte address granularity and 2MB maximum per clip buffer. * Supports expandable rate buffer size selectable from 4K to 64K (in 4K increments). * Uses a re-locatable rate buffer region, with a programmable base register (128-byte location granularity). * Has a re-locatable PTS Value and Ancillary data region, using a programmable base register with 128byte location granularity.
Architecture and Subsystem Information
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* Uses a locatable Audio Temporary Data and Decoded Audio Data Bank region (programmable base register with 128-byte location granularity with additional offset register). * Includes 256x and 512x DAC sampling clock frequency configurations. * Has a programmable stream ID register with corresponding 8-bit enable field. * Provides three PCM output formats in 16- or 20-bit precision: - I2S - Left-justified - Right-justified * Performs audio bitstream error concealment, either by frame repeats or muting, due to loss of synchronization or detection of CRC errors. * Performs MPEG error checking using frame size calculation for each frame. * Provides a programmable interface that supports the following: - Play, stop, and mute - Rate buffer purge to support channel and mode changes - Provides compressed buffer empty/full indicators - Synchronization enable/disable for PTS-STC comparison - Provides buffer fullness value * Includes SPDIF meeting IEC61937 specs. * Supports enhanced IEC61937 S/P DIF Channel Status bit by including 16 SPDIF Channel Status bits, with host control over most of the bits. * Inserts host-controlled validity bit into SPDIF sub-frame via DCR register. * Performs audio attenuation in 64 steps, with smooth transitions between steps. * Provides tone generation with up to 128 generated tones at 31 different durations with seven levels of attenuation via processor command. * Supports automated channel change. * Supports automated time base change. NTSC/PAL Digital Encoder Unit with Macrovision Copy Protection1 The multi-standard Digital Encoder converts digital audio/video data into analog National Television System Committee (NTSC) or Phase Alternate Line (PAL) data output formats (see Macrovision Licensing on page 3). It provides up to six concurrent analog video outputs, including S-Video, composite video, YPbPr, and RGB. The encoder is compatible with SCART connectors, with support for Macrovision Copy Protection Revision 7. Analog outputs are driven by 10-bit D/A converters, operating at 27 MHz. The outputs drive standard video levels into 75- loads. It supports closed caption, teletext insertion, and Line 23 WSS (Wide-screen Signaling) per ITU-R BT.1119. There is a switchable pedestal with gain compensation. Playback of synchronized video data can be locked to the incoming composite video stream.
1. This feature is available only on STB02101, Macrovision license required.
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Additional Interfaces
External Graphics and Video (EGV) Port External Graphics and Video (EGV) ports provide flexibility for interfacing external graphics and video components. When the EGV is used as an output, its signals may be routed to an external graphics device or DENC. When used as an input, either the internal OSD graphics can be replaced with data from an external graphics device, or external digital video data (from an analog signal converted to digital via DSMD, for example) could replace the internally decoded MPEG video. In the latter case, the external digital video can be merged/blended with the internal OSD graphics.
Peripheral Subsystem
Peripheral Subsystem IBM STB0210x
GPT / PWM Other Subsystems SmartCard IIC 16550 Serial Com Infrared Serial Com GPIO Serial Control Port Modem Interface OPB OPB Bridge
General Purpose Timer The General Purpose Timer (GPT) is an on-chip peripheral bus (OPB) function that provides a separate time base counter and additional system timers beyond those defined in the PPC401B3. Three Inter-Character (IC) time-out timers are also implemented in this functional unit in the GPT. These timers receive the count signal inputs from other units they are timing. Each timer is a 10-bit down counter loaded with a programmable value (TOUT) upon the active edge of the count signal input. Once loaded, the IC timer counts down TOUT number of TCLK cycles until it reaches zero (that is, when the IC timer has expired). When a timer expires, it sets its corresponding bit in the IC interrupt status register. There is a separate time base inside the GPT, distinct from the time base within the PPC401B3. Two event timers capture unique input events and there are two compare timers with unique outputs. Separately configurable and programmable synchronization controls edge detection and output levels. There are two reset inputs, one for the entire GPT unit, and one for the time base.
Architecture and Subsystem Information
PLB0
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Pulse Width Modulation The pulse width modulation (PWM) function produces two square wave outputs with a variable duty cycle under program control. The duty cycle varies from 100 percent to zero percent in steps of 1/256. There is a control register with two bits for each PWM. This register controls the active status of the PWM, and determines what its inactive output level should be. When the PWM control register is set to disable a PWM, the 8bit period counter will be inactive to minimize power. The pulse width modulation portion of the GPT contains two identical blocks, each containing an 8-bit programmable and reloadable down counter and control logic. A time-base generator that is a free-running counter (TCLK based) generates the frequency of the pulse-width modulated output. IInter-Integrated Circuit (IIC) Unit The IIC unit is used to provide a simple to use, highly programmable interface between the OPB and the industry standard IIC serial bus. They provide full management of all IIC bus protocols, compliant with Phillips Semiconductors I2C Specification, dated 1995, and support a fixed VDD IIC interface. It can be programmed to operate as master, as slave, or as both master and slave on the IIC interface. In addition to sophisticated IIC bus protocol management, the IIC provide full data buffering between the OPB and the IIC bus. The IIC unit offers 5 V tolerant I/O for both 100- and 400-kHz operation with 8-bit data transfers and 7-bit and 10-bit address decode/generation. There is one programmable interrupt request signal, two independent 4 x 1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers. Smart Card Interface Unit The Smart Card Interface Unit handles communications between an Integrated Circuit Card and the host CPU. These 5 V tolerant I/O devices have a software-based control structure and are designed for use with asynchronous transmissions. It features hardware activation/deactivation and reset with software overrides and byte-wide FIFO support. It is compatible with ISO/IEC 7816-3 and support T0 and T1 protocols. The Interface Unit support 2-channel DMA with 8-bit memory-mapped registers and hardware error checking. An Inter-Character Time-out Facility provides timing support from the GPT/PWM. 16550 Serial Communication Controller The 16550 Serial Communication Controller is a universal asynchronous receiver/transmitter (UART) with FIFOs, and is compatible with the 16550 part numbers manufactured by National Semiconductor (NS) Corporation. It is also compatible with National Semiconductor 16450 (non-FIFO version). Serial interface characteristics are fully programmable with complete modem control functions and status reporting capability. The controller supports: * 5-, 6-, 7-, or 8-bit characters * Even, odd, or no parity bit generation and detection * 1-, 1.5-, or 2-stop-bit generation * Variable baud rate and a programmable baud rate generator There is also support for two DMA channels with a 16-byte FIFO for transmit/receive path. Internal loopback is provided for diagnostics and an Inter-Character Timeout Facility provides timing support from the GPT/PWM.
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Infrared Serial Communications Controller In addition to standard UART functions, the Serial/Infrared Communications Controller can use an alternate mode (IrDA mode) to transfer and receive infrared characters. IrDA transmissions are specified by the Infrared Data Association (IrDA) Specification 1.1. IrDA mode supports RS-232 and infrared communications up to 1.152 Mbps with automatic insertion/removal of standard ASYNC communication bits. The controller includes: * A programmable baud rate generator * Individual enable for receiver and transmitter interrupts * Internal loopback and auto-echo modes * Full-duplex operation * Programmable serial interface * Status reporting capability * Individual receiver and transmitter DMA support * Auto-handshaking mode for receiver and transmitter * Transmitter pattern generation capability * Serial clock frequency up to 1/2 system clock frequency * Inter-Character Timeout Facility support from the GPT/PWM Modem Interface The Modem Interface provides a glueless communication from the device to and from many standard and economical telephony CODECs (Note: CODECs are the Audio ADC/DAC devices). The PPC401B3 CPU and applicable software can be used to implement an inexpensive interface for a modem. The external interface supports industry standard 4-wire parameters, consisting of transmit data, receive data, clock, and frame sync. Two channels of DMA allow off-loading data from the CPU. The Modem Interface supports digital audio MIC input, status reporting, and interrupt generation. Serial Control Port The Serial Control Port (SCP) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other SCP bus-compatible serial devices. The SCP is a slave device to the OPB bus, and supports a three-wire interface to the serial port (receive, transmit, and clock). It provides a glueless serial interface to many microcontrollers, with clock inversion and reverse data. The port includes a programmable clock rate divider (Sysclk/4 to Sysclk/1024), and bit rate is supported up to 1/4 the frequency of the system clock. General Purpose I/O Controller The General Purpose I/O (GPIO) controller enables the multiplexing of module I/Os, with functions that include programmable open-drain output conversion, registered input and output functions, and simplified GPIO definition.
Architecture and Subsystem Information
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Pin and I/O Information
Pinout Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
LEGEND: VDD33 VDD25 Ground I/O Pin
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Signal Pins Sorted by Signal Name
Signal AUD_VDDA0 AUD_VDDA1 BI_ADDRESS8 (MSB) BI_ADDRESS9 BI_ADDRESS10 BI_ADDRESS11 BI_ADDRESS12 BI_ADDRESS13 BI_ADDRESS14 BI_ADDRESS15 BI_ADDRESS16 BI_ADDRESS17 BI_ADDRESS18 BI_ADDRESS19 BI_ADDRESS20 BI_ADDRESS21 BI_ADDRESS22 BI_ADDRESS23 BI_ADDRESS24 BI_ADDRESS25 BI_ADDRESS26 BI_ADDRESS27 BI_ADDRESS28 BI_ADDRESS29 BI_ADDRESS30 BI_ADDRESS31 (LSB)/BI_WBE1 BI_CS0 BI_CS1 BI_CS2 BI_CS3 BI_DATA0 (MSB) BI_DATA1 Grid (Pin) Position AF15 AE12 AF11 AD10 AE10 AE9 AC9 AE11 AD4 AF4 AE5 AC5 AC7 AD6 AD7 AE8 AD9 AC10 AF9 AF8 AE7 AF6 AF5 AE3 AF3 AF2 AD11 AF13 AB3 AC1 AE19 AD17 Group PLL Analog PWR + GND BI_DATA2 PLL Analog PWR + GND BI_DATA3 Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface BI_DATA4 BI_DATA5 BI_DATA6 BI_DATA7 BI_DATA8 BI_DATA9 BI_DATA10 BI_DATA11 BI_DATA12 BI_DATA13 BI_DATA14 BI_DATA15 BI_DATA16 BI_DATA17 BI_DATA18 BI_DATA19 BI_DATA20 BI_DATA21 BI_DATA22 BI_DATA23 BI_DATA24 BI_DATA25 BI_DATA26 BI_DATA27 BI_DATA28 BI_DATA29 BI_DATA30 BI_DATA31 BI_OE BI_READY Signal Grid (Pin) Position AD16 AD15 AE15 AE16 AE17 AF19 AE18 AC17 AF16 AD14 AF14 AD13 AF18 AE20 AD25 AD23 AE23 AE22 AD19 AF21 AD21 AE26 AE24 AD22 AF22 AC20 AC19 AF20 AF24 AD26 AE13 AC12 Group Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface
Pin and I/O Information
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IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
Signal Pins Sorted by Signal Name (Continued)
Signal BI_RW BI_WBE0 CI_CLOCK CI_DATA0 (MSB) CI_DATA1 CI_DATA2 CI_DATA3 CI_DATA4 CI_DATA5 CI_DATA6 CI_DATA7 (LSB) CI_DATA_ENABLE CLK_VDDA DA_BIT_CLOCK DA_IEC_958 DA_LR_CHANNEL_CLOCK DA_OVERSAMPLING_CLO CK DA_SERIAL_DATA0 DAC1_AGND0 DAC1_AGND1 DAC1_AGND2 DAC1_AVDD0 DAC1_AVDD1 DAC1_AVDD2 DAC1_AVDD3 DAC1_BOUT DAC1_BREF_OUT DAC1_GOUT DAC1_GREF_OUT Grid (Pin) Position AE14 AD12 F26 C25 D24 G23 A24 E26 B24 G26 E24 H24 AC2 P1 M3 M4 P2 R2 D13 B10 D8 B12 B11 D10 C9 B7 A7 A11 C13 Group Bus Interface Bus Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Channel Interface Signal DAC1_ROUT DAC1_RREF_OUT DAC1_VREF_IN DAC2_AGND0 DAC2_AGND1 DAC2_AGND2 DAC2_AVDD0 DAC2_AVDD1 DAC2_AVDD2 DAC2_AVDD3 DAC2_BOUT DAC2_BREF_OUT Grid (Pin) Position C14 A9 C10 B13 B16 D18 A14 C16 D17 C19 A19 B19 B15 D15 C15 B18 B17 C5 B5 C8 B4 C6 C4 B3 A4 A8 A6 A3 AC3 Group Video and Graphics Video and Graphics Video and Graphics DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Video and Graphics Global
PLL Analog PWR + GND DAC2_GOUT Audio Audio Audio Audio Audio DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND Video and Graphics Video and Graphics Video and Graphics Video and Graphics DAC2_GREF_IN DAC2_ROUT DAC2_RREF_OUT DAC2_VREF_IN DV1_DATA0 (MSB) DV1_DATA1 DV1_DATA2 DV1_DATA3 DV1_DATA4 DV1_DATA5 DV1_DATA6 DV1_DATA7 (LSB) DV1_HSYNC DV1_PIXEL_CLOCK DV1_VSYNC G_SYSTEM_CLOCK
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Pin and I/O Information
Page 17 of 39
IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Signal Pins Sorted by Signal Name (Continued)
Signal G_SYSTEM_RST GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GPIO_2 GPIO_3 GPIO_4 Grid (Pin) Position G3 P23 V4 A1 A2 A26 AC4 AC8 AC13 AC18 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF25 AF26 B2 B25 B26 C3 C24 D4 D9 D19 D23 H4 J23 N4 D14 W23 B9 AB26 P26 Global Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground General Purpose I/O General Purpose I/O General Purpose I/O Group GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 GPIO_18 GPIO_19 GPIO_20 GPIO_21 GPIO_22 GPIO_23 GPIO_24 GPIO_25 GPIO_26 GPIO_27 GPIO_28 GPIO_29 GPIO_30 GPIO_31 I2C0_SCL I2C0_SDA INT0 INT1 INT2 INT3 MUX1_0 MUX1_1 MUX1_2 Signal Grid (Pin) Position C23 Y4 AA1 W3 L2 K3 G2 M2 L3 H1 N2 AA25 Y23 A22 D20 C21 B21 B20 A21 A16 B14 A12 C12 C11 J2 AB1 AB2 N1 N3 AC24 C26 AD2 AD1 AB25 AB23 AC26 Group General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O General Purpose I/O Inter-Integrated Circuit ) Inter-Integrated Circuit Interrupt Interrupt Interrupt Interrupt Multiplexed I/O Multiplexed I/O Multiplexed I/O
Pin and I/O Information
Page 18 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
Signal Pins Sorted by Signal Name (Continued)
Signal MUX2_0 MUX2_1 MUX2_2 MUX2_3 MUX3_0 MUX3_1 MUX3_2 MUX3_3 MUX3_4 MUX3_5 MUX3_6 MUX3_7 MUX3_8 MUX3_9 MUX3_10 Reserved (Tie to 3.3V) SC0_CLK SC0_DETECT SC0_IO SC0_RESET SC0_VCC_COMMAND SD1_ADDRESS0 (MSB) SD1_ADDRESS1 SD1_ADDRESS2 SD1_ADDRESS3 SD1_ADDRESS4 SD1_ADDRESS5 SD1_ADDRESS6 SD1_ADDRESS7 SD1_ADDRESS8 SD1_ADDRESS9 SD1_ADDRESS10 SD1_ADDRESS11 SD1_ADDRESS12 SD1_ADDRESS13 (LSB) SD1_CAS Grid (Pin) Position C2 D1 E4 E1 V2 V1 P3 U3 U2 U4 T3 T2 T1 R3 R1 F3 Y2 Y1 W4 W1 W2 M25 N24 P24 M26 L25 M24 K23 K24 J26 H26 J25 L24 K25 L26 R24 Group Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Multiplexed I/O Global Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 Smart Card Interface 0 SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SD1_CLK SD1_CS0 SD1_DATA0 (MSB) SD1_DATA1 SD1_DATA2 SD1_DATA3 SD1_DATA4 SD1_DATA5 SD1_DATA6 SD1_DATA7 SD1_DATA8 SD1_DATA9 SD1_DATA10 SD1_DATA11 SD1_DATA12 SD1_DATA13 SD1_DATA14 SD1_DATA15 (LSB) SD1_DQMH SD1_DQML SD1_RAS SD1_WE SERIAL1/INFRARED_CTS SERIAL1/INFRARED_RTS SERIAL1/INFRARED_RXD SERIAL1/INFRARED_TXD VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 Signal Grid (Pin) Position R23 N26 AA26 Y24 W26 V25 V24 U25 U24 T26 U23 T25 U26 V26 V23 W25 Y25 AA24 P25 T24 N25 R25 F2 D36 G4 C1 AA4 AA23 AC6 AC11 AC16 AC21 D6 D11 D16 D21 Group SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Serial1 / Infrared Serial1 / Infrared Serial1 / Infrared Serial1 / Infrared 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Signal Pins Sorted by Signal Name (Continued)
Signal VDD25 VDD25 VDD25 VDD25 VDD25 VDD25 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Grid (Pin) Position F4 F23 L4 L23 T4 T23 E3 G1 H3 M1 P4 R4 V3 AB4 AD5 AF7 AD8 AF12 Group 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 2.5 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 Signal Grid (Pin) Position AC14 AC15 AD18 AC22 AB24 Y26 W24 R26 N23 M23 J24 E23 C22 A20 A15 D12 D5 B8 C7 Group 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power 3.3 V Power
Pin and I/O Information
Page 20 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance
.
STB0210x Digital Set-Top Box Integrated Controllers
Signal Pins Sorted by Pin Number
Grid (Pin) Position A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 DV1_PIXEL_CLOCK DAC1_BREF_OUT DV1_HSYNC DAC1_RREF_OUT NC DAC1_GOUT GPIO_26 NC DAC2_AVDD0 VDD33 GPIO_24 NC NC DAC2_BOUT VDD33 GPIO_23 GPIO_18 NC CI_DATA3 NC GND NC GND DV1_DATA6 DV1_DATA3 DV1_DATA1 NC DAC1_BOUT VDD33 GPIO_2 Video and Graphics 3.3 V Voltage General Purpose I/O Ground Video and Graphics Video and Graphics Video and Graphics Ground Channel Interface Video and Graphics 3.3 V Power General Purpose I/O General Purpose I/O DAC Analog PWR + GND 3.3 V Power General Purpose I/O Video and Graphics General Purpose I/O Video and Graphics Video and Graphics Video and Graphics Video and Graphics GND GND DV1_VSYNC DV1_DATA7(LSB) Signal Ground Ground Video and Graphics Video and Graphics Group Grid (Pin) Position B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Signal DAC1_AGND1 DAC1_AVDD1 DAC1_AVDD0 DAC2_AGND0 GPIO_25 DAC2_GOUT DAC2_AGND1 DAC2_VREF_IN DAC2_RREF_OUT DAC2_BREF_OUT GPIO_22 GPIO_21 NC NC CI_DATA5 GND GND SERIAL1/INFRARED_TXD MUX2_0 GND DV1_DATA5 DV1_DATA0 DV1_DATA4 VDD33 DV1_DATA2 DAC1_AVDD3 DAC1_VREF_IN GPIO_28 GPIO_27 DAC1_GREF_OUT DAC1_ROUT DAC2_ROUT DAC2_AVDD1 NC NC Channel Interface Ground Ground Serial1 / Infrared Multiplexed IO Ground Video and Graphics Video and Graphics Video and Graphics 3.3 V Power Video and Graphics DAC Analog PWR + GND Video and Graphics General Purpose I/O General Purpose I/O Video and Graphics Video and Graphics Video and Graphics DAC Analog PWR + GND Group DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND DAC Analog PWR + GND General Purpose I/O Video and Graphics DAC Analog PWR + GND Video and Graphics Video and Graphics Video and Graphics General Purpose I/O General Purpose I/O
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Signal Pins Sorted by Pin Number (Continued)
Grid (Pin) Position C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 Signal DAC2_AVDD3 NC GPIO_20 VDD33 GPIO_5 GND CI_DATA0(MSB) INT1 MUX2_1 NC SERIAL1/INFRARED_RTS Serial1 / Infrared GND VDD33 VDD25 NC DAC1_AGND2 GND DAC1_AVDD2 VDD25 VDD33 DAC1_AGND0 GND DAC2_GREF_IN VDD25 DAC2_AVDD2 DAC2_AGND2 GND GPIO_19 VDD25 NC GND CI_DATA1 NC NC MUX2_3 Multiplexed IO Ground Channel Interface DAC Analog PWR + GND Ground DAC Analog PWR + GND 2.5 V Power 3.3 V Power DAC Analog PWR + GND Ground Video and Graphics 2.5 V Power DAC Analog PWR + GND DAC Analog PWR + GND Ground General Purpose I/O 2.5 V Power Ground 3.3 V Power 2.5 V Power General Purpose I/O 3.3 V Power General Purpose I/O Ground Channel Interface Interrupts Multiplexed IO Group DAC Analog PWR + GND Grid (Pin) Position E2 E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 NC VDD33 MUX2_2 VDD33 CI_DATA7 NC CI_DATA4 NC SERIAL1/INFRARED_CTS Reserved (Tie to 3.3V) VDD25 VDD25 NC NC CI_CLOCK VDD33 GPIO_11 G_SYSTEM_RST Channel Interface 3.3 V Power General Purpose I/O Global Serial/Infared Global 2.5 V Power 2.5 V Power Channel Interface 3.3 V Power Multiplexed IO 3.3 V Power Channel Interface Signal Group
SERIAL1/INFRARED_RXD Serial/Infared CI_DATA2 NC NC CI_DATA6 GPIO_14 NC VDD33 GND NC CI_DATA_ENABLE NC SD1_ADDRESS9 NC GPIO_29 NC NC General Purpose I/O SDRAM1 Controller Channel Interface 3.3 V Power Ground Channel Interface General Purpose I/O Channel Interface
Pin and I/O Information
Page 22 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
Signal Pins Sorted by Pin Number (Continued)
Grid (Pin) Position J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L23 L24 L25 L26 M1 M2 M3 M4 M23 M24 M25 M26 N1 N2 N3 N4 N23 N24 N25 GND VDD33 SD1_ADDRESS10 SD1_ADDRESS8 NC NC GPIO_10 NC SD1_ADDRESS6 SD1_ADDRESS7 SD1_ADDRESS12 NC NC GPIO_9 GPIO_13 VDD25 VDD25 SD1_ADDRESS11 SD1_ADDRESS4 SD1_ADDRESS13(LSB) VDD33 GPIO_12 DA_IEC_958
DA_LR_CHANNEL_CLOCK
Signal Ground
Group
Grid (Pin) Position N26 P1 P2 P3 P4 P23 SD1_CS0
Signal
Group SDRAM1 Controller Audio
3.3 V Power SDRAM1 Controller SDRAM1 Controller
DA_BIT_CLOCK
DA_OVERSAMPLING_CLO Audio CK MUX3_2 VDD33 GND SD1_ADDRESS2 SD1_DQMH GPIO_4 MUX3_10 DA_SERIAL_DATA0 MUX3_9 VDD33 SD1_CLK SD1_CAS SD1_WE VDD33 MUX3_8 MUX3_7 MUX3_6 VDD25 VDD25 SD1_DQML SD1_DATA9 SD1_DATA7 NC MUX3_4 MUX3_3 MUX3_5 SD1_DATA8 SD1_DATA6 SD1_DATA5 SD1_DATA10 MUX3_1 MUX3_0 Multiplexed IO Multiplexed IO Multiplexed IO SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Multiplexed IO Multiplexed IO Multiplexed IO 3.3 V Power Ground SDRAM1 Controller SDRAM1 Controller General Purpose I/O Multiplexed IO Audio Multiplexed IO 3.3 V Power SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller 3.3 V Power Multiplexed IO Multiplexed IO Multiplexed IO 2.5 V Power 2.5 V Power SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller
General Purpose I/O
P24 P25
SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller
P26 R1 R2 R3 R4
General Purpose I/O General Purpose I/O 2.5 V Power 2.5 V Power SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller 3.3 V Power General Purpose I/O Audio Audio 3.3 V Power SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Inter-Integrated Circuit General Purpose I/O Inter-Integrated Circuit Ground 3.3 V Power SDRAM1 Controller SDRAM1 Controller
R23 R24 R25 R26 T1 T2 T3 T4 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2
VDD33 SD1_ADDRESS5 SD1_ADDRESS0 SD1_ADDRESS3 I2C0_SCL GPIO_15 I2C0_SDA GND VDD33 SD1_ADDRESS1 SD1_RAS
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Signal Pins Sorted by Pin Number (Continued)
Grid (Pin) Position V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 VDD33 GND SD1_DATA12 SD1_DATA4 SD1_DATA3 SD1_DATA11 SC0_RESET SC0_VCC_COMMAND GPIO_8 SC0_IO GND VDD33 SD1_DATA13 SD1_DATA2 SC0_DETECT SC0_CLK NC GPIO_6 GPIO_17 SD1_DATA1 SD1_DATA14 VDD33 GPIO_7 NC NC VDD25 VDD25 SD1_DATA15 GPIO_16 SD1_DATA0 GPIO_30 GPIO_31 BI_CS2 VDD33 MUX1_1 2.5 V Power 2.5 V Power SDRAM1 Controller General Purpose I/O SDRAM1 Controller General Purpose I/O General Purpose I/O Bus Interface 3.3 V Power Multiplexed IO General Purpose I/O General Purpose I/O SDRAM1 Controller SDRAM1 Controller 3.3 V Power General Purpose I/O Signal Group 3.3 V Power Ground SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller SDRAM1 Controller Smart Card Interface 0 Smart Card Interface 0 General Purpose I/O Smart Card Interface 0 Ground 3.3 V Power SDRAM1 Controller SDRAM1 Controller Smart Card Interface 0 Smart Card Interface 0 Grid (Pin) Position AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 VDD33 MUX1_0 GPIO_3 BI_CS3 CLK_VDDA G_SYSTEM_CLOCK GND BI_ADDRESS17 VDD25 BI_ADDRESS18 GND BI_ADDRESS12 BI_ADDRESS23 VDD25 BI_READY GND VDD33 VDD33 VDD25 BI_DATA9 GND BI_DATA28 BI_DATA27 VDD25 VDD33 GND INT0 NC MUX1_2 INT3 INT2 GND BI_ADDRESS14 VDD33 BI_ADDRESS19 Multiplexed IO Interrupts Interrupts Ground Bus Interface 3.3 V Power Bus Interface Signal Group 3.3 V Power Multiplexed IO General Purpose I/O Bus Interface PLL Analog PWR + GND Global Ground Bus Interface 2.5 V Power Bus Interface Ground Bus Interface Bus Interface 2.5 V Power Bus Interface Ground 3.3 V Power 3.3 V Power 2.5 V Power Bus Interface Ground Bus Interface Bus Interface 2.5 V Power 3.3 V Power Ground Interrupts
Pin and I/O Information
Page 24 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
Signal Pins Sorted by Pin Number (Continued)
Grid (Pin) Position AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 Signal BI_ADDRESS20 VDD33 BI_ADDRESS22 BI_ADDRESS9 BI_CS0 BI_WBE0 BI_DATA13 BI_DATA11 BI_DATA3 BI_DATA2 BI_DATA1 VDD33 BI_DATA20 NC BI_DATA22 BI_DATA25 BI_DATA17 GND BI_DATA16 BI_DATA31 GND GND BI_ADDRESS29 NC BI_ADDRESS16 NC BI_ADDRESS26 BI_ADDRESS21 BI_ADDRESS11 BI_ADDRESS10 BI_ADDRESS13 AUD_VDDA1 BI_OE BI_RW BI_DATA4 Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface PLL Analog PWR + GND Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Ground Bus Interface Bus Interface Ground Ground Bus Interface Group Bus Interface 3.3 V Power Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface 3.3 V Power Bus Interface Grid (Pin) Position AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 BI_DATA5 BI_DATA6 BI_DATA8 BI_DATA0 BI_DATA15 NC BI_DATA19 BI_DATA18 BI_DATA24 GND BI_DATA23 GND BI_ADDRESS31 BI_ADDRESS30 BI_ADDRESS15 BI_ADDRESS28 BI_ADDRESS27 VDD33 BI_ADDRESS25 BI_ADDRESS24 NC BI_ADDRESS8 VDD33 BI_CS1 BI_DATA12 AUD_VDDA0 BI_DATA10 NC BI_DATA14 BI_DATA7 BI_DATA29 BI_DATA21 BI_DATA26 NC BI_DATA30 Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface 3.3 V Power Bus Interface Bus Interface PLL Analog PWR + GND Bus Interface Bus Interface Bus Interface Bus Interface Ground Bus Interface Ground Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface 3.3 V Power Bus Interface Bus Interface Signal Group Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface
STB02_sds_0327.fm.01 March 27, 2000
Pin and I/O Information
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Signal Pins Sorted by Pin Number (Continued)
Grid (Pin) Position AF25 GND Signal Ground Group Grid (Pin) Position AF26 GND Signal Ground Group
Pin and I/O Information
Page 26 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
STB0210x Multiplexed I/O Signal Table
STB0210x has four sets of multiplexed I/O signals: Mux0, Mux1, Mux2, and Mux3. At reset, the multiplexed I/O signals are tristated, unless noted. The muxtiplexed I/O can be selected by column in the following tables. For example, if Input/Output 1 is selected, Input/Output 2 and Input/Output 3 are not available. Blank entries indicate reserved multiplexing.
Multiplexed I/O Signal Table - Mux1
Bit # 00 01 02 Input/Output 1 EDMAC2_ACK EDMAC2_REQ EDMAC2_EOT O I I/O I/O Input/Output 2 EBM_HOLDACK EBM_HOLDREQ EBM_BUSREQ I/O I/O I/O I/O Input/Output 3 IDE_REQ IDE_ACK I O
Multiplexed I/O Signal Table - Mux2
Bit # 00 01 02 03 Input/Output 1 SERIAL0/16550_TXD SERIAL0/16550_RXD SERIAL0/16550_CTS SERIAL0/16550_RTS O I I O I/O SSP_TXD SSP_RXD SSP_CLK SSP_FS Input/Output 2 O I I I/O I/O
Multiplexed I/O Signal Table - Mux3
Bit # Input/Output 1 I/O Input/Output 2 I/O Input/Output 3 SERIAL1/INFRARE D_DSR (through GPIO bit 31 alt rcv 2) SERIAL1/INFRARE D_DTR RW_TMS (through GPIO bit 11 alt rcv 1 RW_TDI (through GPIO bit 12 alt rcv 1) RW_TCK (through GPIO bit 13 alt rcv 1) RW_TDO I/O Input/Output 4 I/O
00
HSP_DATA0
O
I
01
HSP_DATA1
O
O
O
I RT_TS1E
02
HSP_DATA2
O
O
I RT_TS2E
03
HSP_DATA3
O
O
I RT_TS3
04
HSP_DATA4
O
05
HSP_DATA5
O
O
RT_TS4
O
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Pin and I/O Information
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
Multiplexed I/O Signal Table - Mux3 (Continued)
Bit # Input/Output 1 I/O Input/Output 2 I/O Input/Output 3 RW_HALT (through GPIO bit 15 alt rcv 1) SERIAL0/16550_DS R (through GPIO bit 5 alt rcv 3) SERIAL0/16550_DT R SERIAL0/16550_DC D (through GPIO bit 6 alt rcv 3) SERIAL0/16550_RI (through GPIO bit 8 alt rcv 3) I/O Input/Output 4 I/O
O
I RT_TS5
06
HSP_DATA6
O
O
I RT_TS6
07
HSP_DATA7
O
08
HSP_CLOCK
O
O
09
HSP_DATA_ ENABLE
O
I
10
HSP_PACKET_ START
O
I
Pin and I/O Information
Page 28 of 39
STB02_sds_0327.fm.01 March 27, 2000
IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
General Purpose I/O (GPIO)
The following table describes the GPIO bits. For each GPIO bit only one signal can be selected at a time.
Each table row lists the signal associated with each logical GPIO bit number. The first column lists the GPIO bit number. The second column lists the signal connected as input or output to the first alternate GPIO multiplexer. The signal name is listed first, followed by the signal description. The third column gives the direction of the signal listed in column 2. The same format is used for columns 4 through 7. Blank entries indicate reserved GPIO multiplexing. GPIO bit number refers to the device GPIO signal name, not the physical device pin number. After reset all GPIOs are programmed as inputs, with the exception of GPIO0 bit 29 (PWM output), which defaults to an open-drain output, and GPIO bit 14 (JTAG TDO output), which defaults to an output (if BI_DATA[4] is set to `0' during reset).
General Purpose I/O Bits
Bit # 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 DV_TRANSPARENCY_ GATE TTX_REQ I/O AV_CSYNC BI_CS4 SYS_CLK EDMAC0_REQ EDMAC0_ACK SCP_TXD SCP_RXD SCP_CLK PWM0 PWM1 RW_TMS RW_TDI RW_TCK RW_TDO RW_HALT I O O I O O I O O O I I I O I CI_PACKET_START CI_DATA_ERROR TS_REQ GPT_COMP0 GPT_COMP1 SSP_TXD SSP_RXD SSP_CLK SSP_FS SERIAL0/16550_CLK - External SERIAL0/16550 Clock Input BI_CS4 BI_CS5 DV2_PIXEL_CLOCK I I O O O O I I I/O I O O I HSP_ERROR SERIAL1/INFRARED_CLK External SERIAL1/INFRARED Clock Input O I GPT_FreqGenOut BI_CS5 SD1_CS1 O O O INT4 INT5 SERIAL0/16550_DTR SERIAL0/16550_DSR SERIAL0/16550_DCD TS_BCLKEN SERIAL0/16550_RI GPT_CAPT0 BI_CS6 GPT_CAPT1 BI_CS7 BI_CS6 BI_CS7 INT6 INT7 SYS_CLK I I O I I I I I O I O O O I I O Input/Output Mux 1 Type Input/Output Mux 2 Type Input/Output Mux 3 Type
19
I/O
DV2_VSYNC
I/O
STB02_sds_0327.fm.01 March 27, 2000
Pin and I/O Information
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IBM39STB0210x STB0210x Digital Set-Top Box Integrated Controllers
Advance
General Purpose I/O Bits (Continued)
Bit # 20 21 22 23 24 25 26 27 28 29 30 31 Input/Output Mux 1 TTX_DATA DV2_DATA0 (MSB) DV2_DATA1 DV2_DATA2 DV2_DATA3 DV2_DATA4 DV2_DATA5 DV2_DATA6 DV2_DATA7 DENC_PWM_OUTPUT EDMAC1_REQ BI_WBE2 EDMAC1_ACK Type I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O O XPT_PWM_OUTPUT SERIAL1/INFRARED_DTR SERIAL1/INFRARED_DSR BI_WBE3 O O I O Input/Output Mux 2 DV2_HSYNC Type I/O INT8 INT9 I I Input/Output Mux 3 Type
Pin and I/O Information
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Electrical Information
The following tables give the absolute ratings for various electrical characteristics.
Drivers/Receivers
Four types of I/O drivers and receivers are used on the STB0210x device, as follows:
.
I/O Driver Types
Driver/ Receiver Type BP3365 Characteristics 5 V tolerant, no pull-up or pull-down (external pull-up is required) 5 V tolerant, no pull-up or pull-down (external pull-up is required) 3.3 V I/O with pull-up 3.3 V I/O with pull-up Used on I/O signals: G_SYSTEM_RESET, GPIO[2], GPIO[29], SC0_IO, SC0_CLK, SC0_DETECT, SC0_RESET, SC0_VCC_COMMAND, BI_READY I2C0_SDA, I2C0_SCL BI_DATA[0:31] all other digital I/O signals
BP3335 BT3350PU BT3365PU
DC Electrical Characteristics
The table, "DC Electrical Characteristics," gives the absolute ratings for various electrical characteristics. The temperature is 70 C in all cases.
DC Electrical Characteristics
Driver / Receiver Symbol VIH VIL BP3335 VOH VOL VIH VIL BP3365 VOH VOL Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltagec VCC = Min, IOH = 9.0 mA VCC = Min, IOL= 6.0 mA VCC = Min, IOH = 17.0 mA VCC = Min, IOL= 11.0 mA 2.00 -0.602 2.40 0.4 Conditions Min 2.00 -0.602 2.40 0.4 5.501 0.80 Typ Max 5.501 0.80 Units V V V V V V V V
1. Maximum VIH applies to overshoot only. 2. Minimum VIL applies to undershoot only.
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Electrical Information
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Advance
DC Electrical Characteristics (Continued)
Driver / Receiver Symbol VIH VIL BT3350PU VOH VOL VIH VIL BT3365PU VOH VOL BT3350PU, BT3365PU BP3335, BP3365 N/A N/A All All N/A II II ICC ICC330 CI ESD PD Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Maximum Input Current Maximum Input Current Supply Current, 2.5 V Supply Current, 3.3 V Input Capacitance Electro Static Discharge Power Dissipation VCC = Max VCC330 = Max VCC = Nom, VI = Nom TBD 2.5 VCC = Min, IOH = 9.0 mA VCC = Min, IOL= 6.0 mA VIN = 0 V VCC = Min, IOH = 12.0 mA VCC = Min, IOL= 8.0 mA 2.00 -0.602 2.40 0.4 -250 0 TBD TBD 2.6 TBD Conditions Min 2.00 -0.602 2.40 0.4 4.01 0.80 Typ Max 4.01 0.80 Units V V V V V V V V A A mA mA pF V W
1. Maximum VIH applies to overshoot only. 2. Minimum VIL applies to undershoot only.
Electrical Information
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IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
The absolute maximum ratings in the following table are stress ratings only. Operation at or beyond these maximum ratings may cause permanent damage to the device.
.
Absolute Maximum Ratings
Parameter Supply voltage with respect to GND, 2.5 V supply Supply voltage with respect to GND, 3.3 V supply Case temperature under bias Storage temperature Maximum Rating 3.0 V 3.9 V TBD -65 C to 150 C
Operating Conditions The STB0210x Digital Set-Top Box Integrated Controller can interface to either 3.3 V or 5 V technologies. 5 V interfaces are supported only for drivers/receivers supporting 5 V tolerance (see Drivers/Receivers). The range for supply voltages is specified for five-percent margins relative to a nominal 2.5 V and 3.3 V power supply. Note: Device operation beyond the conditions specified in the table below is not recommended. Extended operation beyond the recommended conditions may affect device reliability. Recommended Operating Conditions
Symbol Parameter Min Max Unit
VCC VCC330 TA
Supply Voltage, 2.5 V Supply Voltage, 3.3 V Operating Free Air Temperature
2.38 3.14 0
2.62 3.47 70
V V C
Power Considerations Power dissipation is determined by operating frequency, temperature, and supply voltage, as well as external source/sink current requirements. Recommended Connections Power and ground pins should all be connected to separate power and ground planes in the circuit board to which the STB0210x is mounted. Unused input pins must be tied inactive, either high or low.
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Electrical Information
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Advance
Recommended Connections for Analog I/O Pins
DAC1_AVDD0 DAC1_AVDD1 DAC1_AVDD2 DAC1_AVDD3 DAC2_AVDD0 DAC2_AVDD1 DAC2_AVDD2 DAC2_AVDD3
B12 B11 D10 C9 A14 C16 D17 C19 1 nF 1 nF .1 mF .1 mF .1 mF .1 mF .1 mF 22 mF 1 nH 2.5 V
DAC1_GREF_OUT DAC2_GREF_OUT DAC1_RREF_OUT DAC2_RREF_OUT
c13 D13 A9 B18 784 784 (For a 75 W DAC Output Load)
DAC1_BREF_OUT DAC2_BREF_OUT
A7 B19 1 nF 1 nF
CLK_VDDA
AC2 .1 mF
1.2 mF
2.5V
AUD_VDDA0 AUD_VDDA1
AF15 AE12 .1 mF 5K
1.2 mH 2.5 V
I/O Timing Diagrams
AC Specification Timings are being developed and will be added when available. They should be similar to STB03xxx. Note:
Electrical Information
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Additional Timing Information
Interface Timing Information Compliant with Philips Semiconductors I2C Specification, dated 1995. Interface is asynchronous Direct connect Compatible with ISO/IEC 7816-3. Interface is asynchronous Direct connect Functionally identical to National Semiconductor NS16450 in character mode (after reset). Interface is asynchronous External transceiver logic is required Functionally identical to IBM PowerPC403TM Serial Port Unit (SPU) (after reset). Compatible with the IrDA Specification 1.1 IrDA 1.0 SIR with data rates up to 115.2 Kbps IrDA 1.1 FIR with data rates up to 1.152 Mbps Interface is asynchronous External transceiver logic is required Inputs are asynchronous External DMA request inputs are asynchronous Capture timer inputs are asynchronous Interface is asynchronous Compatible with IBM RISCWatch probe Direct connect to probe Contact your IBM Applications Engineer for more information Compatible with IBM RISCTrace probe Direct connect to probe Contact your IBM Applications Engineer for more information
IIC
Smart Card (SC)
Serial0/16550
Serial1/Infrared
External Interrupts DMA GPT External Bus Master
RISCWatch
RISCTrace
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Electrical Information
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Advance
Mechanical Information
Package Diagram
Top of Package (BGA Side Down)
Digital Set-Top Box Integrated Controller
IBM P/N
PowerPC(R)
XXXXXXX ZZWWMMMM Date Code
0.25 C 0.15 C
IBM39 STB0210x xxx xxx OEM P/N A B
35
31.75 0. 20 AF AEAD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1.27
C
35
31.75 1.27
(352X 0.75 0.15 SOLDER BALL 0.30 MC MC A B 0.15
Bottom of Package (BGA Side Up)
Mechanical Information
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IBM39STB0210x Advance STB0210x Digital Set-Top Box Integrated Controllers
Development Support
With IBM tools and the IBM PowerPC Embedded Tools Program, you receive the support you need to develop and debug your STB applications quickly.
IBM Tools
IBM offers Windows(R) 95/98-hosted development tools for STB applications that include: * STB and processor reference design and evaluation kits, including board, compiler, debugger, ROM source, schematics, etc. * RISCWatch debugger, with in-circuit, ROM monitor, RTOS-aware debugging and real-time non-invasive trace capability * Metaware High C/C++ compiler, highly optimized for the PowerPC processors
Debug
The STB0210x facilitates development through its JTAG test access port. With IBM RISCWatch or other third-party debugger on a workstation, you can single-step the processor and interrogate the internal processor state. Additionally, the real-time debug port supports tracing the executed instruction stream out of the instruction cache. The trace status signals provide trace information in real-time instruction trace debug mode. This mode does not alter the performance of the processor.
Third-Party Tool Support
Through the IBM PowerPC Embedded Tools Program, you have access to hundreds of tools offered by over 75 industry-leading vendors. Often, the tools you currently use support PowerPC embedded processor products, such as the IBM STB010XX Digital Set-Top Box Integrated Controllers. For a list of the tools that are offered, visit IBM's tool support Web page at: http://www.chips.ibm.com/products/powerpc/tools/
Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design.
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Development Support
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Advance
Revision Log
Revision March 24, 2000 March 27, 2000 Initial release (revision 00). Update to GPIO Table (revision 01) Contents of Modification
Revision Log
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Copyright and Disclaimer
(c) Copyright International Business Machines Corporation 2000. All Rights Reserved Printed in the United States of America February 2000
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM IBM Logo CoreConnect PowerPC logo PowerPC 401
Windows is a trademark of Microsoft Corporation in the United States and/or other countries.
Other company, product, and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM's product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. Product name is subject to change.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351
The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com
STB02_sds_0327.fm.01 March 27, 2000

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